Metal S/D FETs promise to improve the scalability, variability, and performance of ultra-thin-body complementary metal oxide semiconductor (CMOS) devices. There are two basic types of metal S/D devices. In the more traditional design, a relatively large Schottky barrier (ΦB) at the source is used to control the net rate of carrier injection into the channel. While this mode may provide relatively large on-off current ratios, low drain induced barrier lowering (DIBL), and also high sub-threshold slopes, the drive current suffers. See J. Larson and J. Snyder, “Overview and status of metal S/D Schottky barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1046-1056, May 2006. The alternative is to minimize the Schottky barrier between the metal and the band corresponding to the channel charge carriers, and use the channel conductance to control current, emulating the operation mode of a doped S/D FET. See D. Connelly, C. Faulkner, and D. E. Grupp, “Performance advantage of metal source/drain in ultra-thin-body silicon-on-insulator and dual-gate CMOS,” IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 134-1 345, May 2003.
Taking the example of an n-channel FET (n-FET), minimizing (ΦB) to the conduction band also maximizes ΦB to the valence band, which reduces leakage currents under negative gate-to-source bias. See, e.g., D. Connelly, et al., “Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018,” in 2005 IEEE IEDM Tech. Digest, pp. 972-975, December 2005. Near-zero Schottky barriers may be possible to the valence band of Ge (A. Dimoulas, P. Tsipas, and A. Sotiropoulos, “Fermi-level pinning and charge neutrality level in germanium,” Appl. Phys. Lett., vol. 89, p. 252110, 20 Dec. 2006), but in most cases, minimizing the Schottky barrier is a technological challenge. To improve drive current, an electric field enhancement of current across the junction is needed. One such method is to use gate fields by overlapping the source and drain with the gate, e.g., J. Snyder, C. Helms, and Y. Nishi, “Experimental investigations of a PtSi source and drain field emission transistor,” Appl. Phys. Lett., vol. 67, p. 1420, 4 Sep. 1995. However, this approach is unfavorable for scaled devices (see D. Connelly, C. Faulkner, and D. E. Grupp, “Optimizing Schottky S/D offset for 25 nm dual-gate CMOS performance,” IEEE Electron Device Lett., vol. 24, no. 6, pp. 411-413, June 2003), where carefully optimized S/D-to-gate underlap is preferred. Another approach to increasing the electric field is dopant segregation (see A. Kinoshita et al., “Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique,” in 2004 IEEE symposium on VLSI Technology, Tech. Digest, 15-17 Jun. 2004, pp. 168-169.) Another approach uses the proximity of a low (n-FET) or a high (p-FET) work function metal to induce an inversion layer adjacent to the metal-semiconductor junction and so reduce the resistance of the junction (D. Connelly et al., “Improved short-channel FET performance with virtual extensions,” IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 146-152, January 2006).
In addition to the S/D-to-gate underlap, the S/D shape can also be optimized, for example by forming a source and drain on {111} facets to create a “trapezoidal body” for a single-gated planar FET to reduce short channel effects. The use of a tetramethylammonium hydroxide (TMAH) solution etch to expose {111} facets and thus form angled sidewalls that slope inward towards the gate was disclosed by Grupp and Connelly in a process to fabricate deposited metal S/D FETs. See FIG. 2 of U.S. Pat. No. 6,833,556, reproduced herein as FIG. 10. Transistor 1000 is formed on a substrate 1002 and contains a channel 1004 that is proximate to a source 1006 and a drain 1008 at single faceted sidewalls 1010 and 1012, respectively. As shown in the detail, the junctions between the S/D and the channel include a separation layer 1014 and a passivation layer 1016. The transistor also includes a gate 1018 surrounded by an insulator 1020. While the single-faceted design may work with a single gate, in dual-gate designs such as FinFETs, it would break the symmetry between the two channels.
Bohr et al., U.S. Pat. No. 7,494,858, describes a transistor 1100 with a tip profile in which the entire S/D region is formed by a single, selective wet etch. As shown in FIG. 11, which is a reproduction of FIG. 2 of the '858 patent, this wet etch forms S/D regions 1102, 1104, with a single facet of the {111} family 1106 and a single facet of the {100} family 1108. That is, the etch leads to two different kinds of crystallographic planes, one from the {010} family and the other from the {111} family. Bohr et al. further elaborate that their inversion layer, i.e., the channel 1110, is aligned only with a single {100} facet in their device. In transistor 1100, a gate 1112 is formed and patterned atop an insulator 1114, and on each side of the gate there is a sidewall spacer 1116.
Luo et al., U.S. Pat. No. 7,485,524, describes a crystallographic etching of S/D regions, but assumes a bulk transistor where the starting wafer is a {110} surface, the S/D region is etched using a wet etch, and the sidewall surfaces are one or more {100} planes in silicon. Subsequent filling of the S/D regions with epitaxially grown semiconductor material results in “slanted” upper surfaces that are far removed from the channel.
Linden et al., U.S. Pat. No. 6,946,350, and Linden et al., U.S. Pat. No. 7,060,576, each describe methods for highly selective faceting of the S/D regions in CMOS devices. However, there is no description of such a device wherein a surface of a semiconductor channel proximate to the S/D is formed of two or more well-defined crystallographic surfaces of common orientation (i.e., surfaces of similar atomic arrangement, of the same crystallographic family) that meet at an angle such that a surface of the S/D proximate to the channel forms an angled feature.
Keating et al., U.S. Pat. No. 7,060,576, describes a transistor structure in which the S/D region is recessed underneath the gate using a wet etch to form a single (111) plane as an S/D-to-channel interface. The recess is subsequently filled with doped SiGe. The structure does not include a S/D-to-channel interface having two or more well-defined crystallographic surfaces of equivalent lattice planes that meet at an angle.